1. Field of the Invention
The present invention relates to a flip-chip packaging method, and more particularly, to a method of mounting a chip onto a flip-chip packaging substrate.
2. Description of the Prior Art
In recent years, as portable electronic products such as notebook computers, personal digital assistants (PDA), and cellular phones become smaller and as the function of central processing unit (CPU) and memory modules become more complex, the manufacturing of semiconductors has also advanced in a direction of high density packaging, thereby developing numerous packaging products with the characteristics of having small size and light weight. In contrast to the conventional packaging structure, the flip chip (FC) packaging structure widely used today has the advantage of fast heat dissipation, low inductance, multi-terminal property, and smaller size chips. By enhancing and expanding these advantages, the flip chip packaging technique has the potential to grow exponentially in the near future.
Please refer to FIG. 1. FIG. 1 is a perspective diagram showing the cross-section of a flip-chip packaging structure 30 according to the prior art. As shown in FIG. 1, the conventional flip chip packaging structure 30 includes a die 32, in which the die 32 further includes an active surface 34 and a plurality of connecting pads (not shown) disposed for the active surface 34. Additionally, the flip chip packaging structure 30 includes a substrate 36, in which the upper surface and bottom surface of the substrate 36 includes a solder mask layer 38 and 45. Preferably, the substrate 36 is a multi-layer substrate and the solder mask layer 38 includes a plurality of openings for exposing the bump pad of the substrate 36.
During the process of packaging, the active surface 34 of the die 32 is positioned towards the solder mask layer 38 of the substrate 36, such that the position of each connecting pad (not shown) is arranged corresponding to the position of each bump pad (not shown). Next, a plurality of solder balls 42 are disposed between the connecting pads and the bump pads for providing a physical connection between each connecting pad and each bump pad. Depending on fabrication processes and design of the devices, an under bump metallurgy layer (not shown) is often utilized as a adhesive layer, resist layer, wetting layer, or a conductive layer between each connecting pad and the solder ball 42. In the same time, the die 32 also includes at least an integrated circuit (IC) in the level of very large scale integration (VLSI) or ultra large scale integration (ULSI), in which the integrated circuits are electrically connected to the substrate 36 through the connecting pads, solder balls 42, and bump pads described previously.
Additionally, the flip chip packaging structure 30 also includes an underfill material layer 44, in which the underfill material layer 44 is formed to completely fill the gap between the substrate 36 and the die 32 for protecting the flip chip packaging structure 30 from influences from the external environment and for reducing the stress at the connecting end of the solder ball 42. Preferably, the solder mask layer 45 includes a plurality of openings for exposing the solder ball pad 46 of the substrate and the flip chip packaging structure 30 also includes a plurality of solder balls 48 formed under each solder ball pad 46.
Essentially, the conventional method of fabricating a flip chip package usually requires many times reflow process, which ultimately brings challenges to the reliability of the final product. Additionally, phenomenon such as substrate cracks will often result due to incompatible coefficients of thermal expansion (CTE) between the substrate and the underfill layer, thereby influencing the quality of the product. Moreover, one other major disadvantage of the conventional method lies in the fact that the processed substrates are shipped in a one-piece manner to the packaging facility for further packaging. By packaging the finished substrate one piece at a time, the overall cost for acquiring all the necessary equipment and facilities will increase and the final production yield will also be significantly limited.